Joel Emer - Concepedia

Author

Joel Emer

Also Known As

Collin, Teodoro Fields, Emer, Joel, Emer, Joel S., J. Emer, J. S. Emer, J.S. Emer, Joel Emer, Joel S Emer, Joel S. Emer, Matthew Fojtik

279

Publications

25.5K

Citations

H-Index

132

Concepts

All Affiliations

Massachusetts Institute of Technology Intel (United States)Nvidia (United States)Nvidia (United Kingdom)Digital Wave (United States)

About

Joel Emer is an author at Massachusetts Institute of Technology specializing in engineering, computer engineering, and computer science.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	62	115	24.1K
2	Management	3	3	103
3	Arts	1	1	12
4	Civil Engineering	1	1	23
5	Communication	1	1	12

Joel Emer

128

Publications

24.5K

Citations

H-Index

Page 1

	Year	Citations
Efficient Processing of Deep Neural Networks: A Tutorial and Survey Vivienne Sze, Yu‐Hsin Chen, Tien-Ju Yang, Proceedings of the IEEE Convolutional Neural NetworkDeep Neural NetworksMachine VisionMachine LearningData Science	2017	3.8K
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks Yu-Hsin Chen, Tushar Krishna, Joel Emer, IEEE Journal of Solid-State Circuits Machine VisionRow StationaryEngineeringHardware AccelerationAccelerator Chip	2016	3K
Eyeriss Yu‐Hsin Chen, Joel Emer, Vivienne Sze ACM SIGARCH Computer Architecture News Energy ConsumptionSpatial ParallelismConvolutional Neural NetworkEngineeringMachine Learning	2016	1.2K
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices Yu-Hsin Chen, Tien-Ju Yang, Joel Emer, IEEE Journal on Emerging and Selected Topics in Circuits and Systems Convolutional Neural NetworkEngineeringMachine LearningComputer ArchitectureEyeriss V2	2019	1K
SCNN Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Sparse CnnConvolutional Neural NetworkEngineeringMachine LearningData Science	2017	918
Exploiting choice Dean M. Tullsen, Susan J. Eggers, Joel Emer, Hardware SecurityEngineeringHigh-performance ArchitectureThroughput GainsComputer Architecture	1996	779
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor S. Mukherjee, Christopher Weaver, Joel Emer, EngineeringHardware Verification LanguageRaw Error RateComputer ArchitectureSoftware Engineering	2004	638
High performance cache replacement using re-reference interval prediction (RRIP) Aamer Jaleel, Kevin B. Theobald, Simon C. Steely, Web CacheRe-reference Interval PredictionLru Replacement PolicyMemory ArchitectureEngineering	2010	637
Adaptive insertion policies for high performance caching Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, EngineeringComputer ArchitectureHardware SecuritySystems EngineeringLru Insertion Policy	2007	631
Timeloop: A Systematic Approach to DNN Accelerator Evaluation Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Architecture Design SpaceDeep Neural NetworksEngineeringMachine LearningHardware Acceleration	2019	513

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