Energy-efficient Hardware Acceleration

Energy-Efficient Hardware Acceleration is a hardware acceleration paradigm that leverages reconfigurable FPGA architectures to execute specialized computational tasks with minimal energy consumption per operation, distinguished by its co-optimization of circuit-level design, resource allocation, and workload-specific parallelism to achieve superior energy efficiency compared to general-purpose or fixed-function alternatives.

1.2K

Publications

58.6K

Citations

4K

Authors

735

Institutions

Publications per year

2017–2026

755

Authors

4K

  1. LB
    Luca Benini

    University of Bologna, Italy

    31 publications · 1.7K citations

    20

    h-index

  2. JC
    Jason Cong

    University of California, Los Angeles, United States

    21 publications · 1.7K citations

    18

    h-index

  3. DR
    Davide Rossi

    University of Bologna, Italy

    16 publications · 815 citations

    15

    h-index

  4. MI
    Mohsen Imani

    University of California San Diego, United States

    16 publications · 617 citations

    14

    h-index

  5. WL
    Wayne Luk

    Imperial College London, United Kingdom

    16 publications · 729 citations

    14

    h-index

1–5 of 4K

Venues

  1. IEEE Journal of Solid-State Circuits

    27 publications · 4.7K citations

    21

    h-index

  2. IEEE Micro

    23 publications · 1.4K citations

    19

    h-index

  3. 18

    h-index

  4. arXiv (Cornell University)

    Repository · 29 publications · 1.9K citations

    18

    h-index

  5. 18

    h-index

1–5