Concepedia

Network-on-chip Architectures

Network-On-Chip Architectures is a systematic framework for organizing on-chip communication in parallel computing systems by employing a packet-switched network to interconnect intellectual property cores, distinguished from traditional bus-based or point-to-point interconnects through its scalable, modular, and concurrent data transmission capabilities.

2.5K

Publications

123.6K

Citations

4.6K

Authors

963

Institutions

Publications per year

2017–2026

381

Parents

Publications

2.5K

Route packets, net wires

William J. Dally, Brian Towles · 2001 · 3.2K citations

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DART

Patrice Godefroid, Nils Klarlund, Koushik Sen · ACM SIGPLAN Notices · 2005 · 2.1K citations

, , +15

DART

Patrice Godefroid, Nils Klarlund, Koushik Sen · 2005 · 1.5K citations

, , +15

A network on chip architecture and design methodology

Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen et al. · 2003 · 1.2K citations

, , +17

Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices

Yu-Hsin Chen, Tien-Ju Yang, Joel Emer et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 2019 · 1.1K citations · Full text

, , +16

1–5 of 2.5K

Authors

4.6K

  1. RM
    Radu Mărculescu

    Carnegie Mellon University, United States

    55 publications · 6.4K citations

    37

    h-index

  2. LB
    Luca Benini

    University of Bologna, Italy

    53 publications · 4.6K citations

    34

    h-index

  3. KG
    Kees Goossens

    Eindhoven University of Technology, Netherlands

    48 publications · 4.1K citations

    34

    h-index

  4. GD
    Giovanni De Micheli

    École Polytechnique Fédérale de Lausanne, Switzerland

    42 publications · 5.2K citations

    33

    h-index

  5. LP
    Li-Shiuan Peh

    Princeton University, United States

    39 publications · 3.8K citations

    28

    h-index

1–5 of 4.6K

Institutions

963

  1. Carnegie Mellon University

    Pittsburgh, United States

    47 h-index

    193 publications

    20.4K citations

  2. Stanford University

    Stanford, United States

    37 h-index

    115 publications

    29.3K citations

  3. University of Bologna

    Bologna, Italy

    37 h-index

    120 publications

    9.7K citations

  4. Intel (United States)

    Santa Clara, United States

    30 h-index

    174 publications

    20.2K citations

  5. KTH Royal Institute of Technology

    Stockholm, Sweden

    28 h-index

    168 publications

    13.1K citations

  6. École Polytechnique Fédérale de Lausanne

    Lausanne, Switzerland

    28 h-index

    83 publications

    5K citations

  7. Pennsylvania State University

    State College, United States

    28 h-index

    191 publications

    17.2K citations

  8. Princeton University

    Princeton, United States

    26 h-index

    77 publications

    9.1K citations

1–8 of 963

Venues

  1. IEEE Transactions on Computers

    50 publications · 4.5K citations

    31

    h-index

  2. 29

    h-index

  3. 28

    h-index

  4. IEEE Micro

    33 publications · 2.3K citations

    23

    h-index

  5. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 41 publications · 2.1K citations

    23

    h-index

1–5