Pai-Yu Chen - Concepedia

Author

Pai-Yu Chen

Arizona State University ORCID

Also Known As

Pai-Yu Chen

Publications

6.2K

Citations

H-Index

Concepts

All Affiliations

Arizona State University Tsinghua University The University of Texas at Austin Georgia Institute of Technology National University of Defense Technology

About

Pai-Yu Chen is an author at Arizona State University specializing in engineering, computer engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	31	43	5.3K
2	Computer Engineering	30	41	4.6K
3	Computer Science	20	23	2.4K
4	Social Sciences	14	15	2.2K
5	Applied Physics	11	11	1.6K

Pai-Yu Chen

Publications

6.1K

Citations

H-Index

Page 1

	Year	Citations
SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations Shinhyun Choi, Scott H. Tan, Zefan Li, Nature Materials Reproducible High PerformanceEngineeringPhysicsApplied PhysicsMemory Device	2018	674
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning Pai-Yu Chen, Xiaochen Peng, Shimeng Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	2018	604
Ferroelectric FET analog synapse for acceleration of deep neural network training Matthew Jerry, Pai-Yu Chen, Jianchi Zhang, EngineeringNeural Networks (Machine Learning)Synaptic TransmissionEmerging Memory TechnologyPhase Change Memory	2017	554
Emerging Memory Technologies: Recent Trends and Prospects Shimeng Yu, Pai-Yu Chen IEEE Solid-State Circuits Magazine Non-volatile MemoryMemory TechnologiesEngineeringEmerging Memory TechnologyComputer Architecture	2016	521
NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures Pai-Yu Chen, Xiaochen Peng, Shimeng Yu EngineeringNeural Networks (Machine Learning)Computer ArchitectureNeurochipSocial Sciences	2017	405
Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design Pai-Yu Chen, Shimeng Yu IEEE Transactions on Electron Devices Non-volatile MemoryEngineeringRram Retention PropertyEmerging Memory TechnologyRram Devices	2015	344
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors Win-San Khwa, Jiajing Chen, Jiafang Li, EngineeringComputer ArchitectureMulti-channel Memory ArchitectureHigh-performance ArchitectureSparse Neural Network	2018	240
Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect Shimeng Yu, Pai-Yu Chen, Yu Cao, EngineeringNeuro-inspired ArchitectureComputational NeuroscienceApplied PhysicsComputer Engineering	2015	216
Binary neural network with 16 Mb RRAM macro chip for classification and online training Shimeng Yu, Zhiwei Li, Pai-Yu Chen, NeurochipEngineeringMachine LearningPattern RecognitionMb Rram	2016	214
Mitigating effects of non-ideal synaptic device characteristics for on-chip learning Pai-Yu Chen, Binbin Lin, I‐Ting Wang, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) EngineeringMachine LearningNeural Networks (Machine Learning)NeurochipSocial Sciences	2015	214

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