NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures

TLDR

NeuroSim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of system‑level learning accuracy and hardware performance metrics. This work studies the impact of analog eNVM non‑ideal device properties and benchmarks trade‑offs among SRAM, digital, and analog eNVM array architectures for online learning and offline classification. The framework is hierarchically organized from device to circuit to algorithm levels and is used to evaluate analog eNVM effects and compare array trade‑offs. NeuroSim+ version 1.0 source code is publicly available on GitHub. Code is hosted at https://github.com/neuro-sim/MLP.

Abstract

NeuroSim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics. It has a hierarchical organization from the device level (transistor technology and memory cell models) to the circuit level (synaptic array architectures and neuron periphery) and then to the algorithm level (neural network topologies). In this work, we study the impact of the “analog” eNVM non-ideal device properties and benchmark the trade-offs of SRAM, digital and analog eNVM based array architectures for online learning and offline classification. The source code of NeuroSim+ version 1.0 is publicly available at https ://github. co m/neuro sim/MLP Neuro Sim.