Engineering Research Express · 2019 · 11 citations · 26 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDevice CharacterizationDevice ModelingDevice SimulationIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsTiming AnalysisCapacitanceField-effect Transistor SimulationGate Delay ModelingInverter DesignInvertersLookup Table DesignMetal-oxide-semiconductor Field-effect Transistor ModelingVerilog-ams
In this work, a Lookup table based verilog-A model is employed in cadence to evaluate the performance of the chain of inverters and 6-T SRAM cell based on double gate Tunnel-field-effect transistor (DGTFET). In order to drive large capacitance with fixed number of inverters stages with constant width of N type DGTFET (Wn), it is found that the time delay performance of the inverter chain depends on the ratio of width of P type DGTFET of nth stage (Wpn) to width of P type DGTFET of n-1th stage (Wpn−1). Simulation results investigated that the time delay is minimized to 0.265 ns for Wpn/Wpn−1 = 3. The impact of cell ratio (CR) and pull up ratio (PR) on the read stability and write ability of 6-T SRAM cell are investigated by using N curve simulations. It is observed that, increasing CR and PR strengthens the read stability and degrades the write ability of 6-T SRAM cell.
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Low-subthreshold-swing tunnel transistors
Qin Zhang, Wei Zhao, Alan Seabaugh · IEEE Electron Device Letters · 2006 · 652 citations
Tunneling Field-Effect Transistor: Capacitance Components and Modeling
Yue Yang, Xin Tong, Pengfei Guo et al. · IEEE Electron Device Letters · 2010 · 247 citations