Verilog-ams
Verilog-AMS is a hardware description language extension that integrates analog and mixed-signal behavior modeling with digital logic simulation, distinguished by its support for continuous-time and event-driven domains within a unified framework.
45
Publications
1.1K
Citations
152
Authors
52
Institutions
Publications per year
2017–2026
6
Variants
Verilog-a/ms
Parents
45
ADMS-automatic device model synthesizer
L. Lemaître, Colin C. McAndrew, Silke Hamm · 2003 · 61 citations
Engineering, Computer Engineering, Electrical Engineering +17
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52
Indian Institute of Technology Kharagpur
Kharagpur, India
2 h-index
6 publications
150 citations
Motorola (United States)
Schaumburg, United States
2 h-index
3 publications
93 citations

University of Arkansas at Fayetteville
Fayetteville, United States
2 h-index
9 publications
126 citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
2 h-index
3 publications
242 citations
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
Paris, France
2 h-index
11 publications
202 citations
CEA Grenoble
Grenoble, France
2 h-index
11 publications
202 citations
Cadence Design Systems (United States)
San Jose, United States
2 h-index
4 publications
124 citations
Aristotle University of Thessaloniki
Thessaloniki, Greece
2 h-index
4 publications
66 citations
1–8 of 52
2 publications · 212 citations
2
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2 publications · 32 citations
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1 publications · 14 citations
1
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1 publications · 10 citations
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Conference · 1 publications · 14 citations
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