Impact of interface traps/defects and self‐heating on the degradation of performance of a 4H‐SiC VDMOSFET

Abstract

The reliability of silicon carbide metal oxide semiconductor field‐effect transistors remains a challenge in power applications and relates to the SiO 2 –SiC interface. The presence of unwanted interface traps/defects degrades the device performance. The impact of acceptor traps/defects on the performance of a 4H‐SiC vertical Diffused Metal Oxide Semiconductor Field Effect Transistor (DMOSFET) with a breakdown voltage of 1700 V is investigated. ‐ and ‐ characteristics were simulated, using a drift‐diffusion model coupled to Fourier heat equations, and are in a good agreement with experimental results. The presence of interface traps/defects were shown to produce degradation of threshold voltage, but the impact diminishes as temperature increases. A threshold voltage shift of 3.5 V occurs for a trap concentration of 2 × 10 13 cm– 2 /eV at room temperature. The transfer characteristics obtained from electro‐thermal modelling show a larger degradation than those at a constant temperature. This degradation increases with the drain bias increase. The threshold voltage from the electro‐thermal simulations is 5 V compared to 4 V observed in constant 423 K temperature simulations at. Finally, the interface traps/defects increases breakdown voltage exhibiting a strong dependency on the trap density and their energy decay characteristics.