20–80nm Channel length InGaAs gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63mV/dec

Abstract

In this paper, 20nm-80nm channel length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) InGaAs gate-all-around (GAA) nanowire MOSFETs with record high on-state and off-state performance have been demonstrated by equivalent oxide thickness (EOT) and nanowire width (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</sub> ) scaling down to 1.2nm and 20nm, respectively. SS and DIBL as low as 63mV/dec and 7mV/V have been demonstrated, indicating excellent interface quality and scalability. Highest I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 0.63mA/μm and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> = 1.74mS/μm have also been achieved at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.5V, showing great promise of InGaAs GAA technology for 10nm and beyond high-speed low-power logic applications.