Heng Wu

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

J. Zhang, Julien Frougier, Andrew Greene et al. · 2019 · 97 citations

Engineering, Electrical Engineering, Materials Science +17

A 14 nm Embedded STT-MRAM CMOS Technology

D. Edelstein, Michael Rizzolo, Devika Sil et al. · 2020 · 58 citations

Engineering, Computer Engineering, Electrical Engineering +16

Size-Dependent-Transport Study of $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ Gate-All-Around Nanowire MOSFETs: Impact of Quantum Confinement and Volume Inversion

Jiangjiang Gu, Heng Wu, Yiqun Liu et al. · IEEE Electron Device Letters · 2012 · 54 citations · Full text

Engineering, Electrical Engineering, Materials Science +17

First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters

Heng Wu, Wangran Wu, Mengwei Si et al. · 2015 · 45 citations

Engineering, Electrical Engineering, Microelectronics +16

20–80nm Channel length InGaAs gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63mV/dec

Jiangjiang Gu, Xinwei Wang, Heng Wu et al. · 2012 · 37 citations

Engineering, Electrical Engineering, Materials Science +17