28nm Fault-Tolerant Hardening-by-Design Frequency Divider for Reducing Soft Errors in Clock and Data Recovery

Abstract

A fault-tolerant hardening-by-design frequency divider has been proposed for clock and data recovery in a 28-nm CMOS process. By means of the mandatory updating mechanism, the proposed divider can update the state of the D flip-flops from an error state to a correct state so as to avoid single-event transient (SET) accumulation in different finite-state machines (FSMs). Our proposed divider also does not destroy the original structure and can, thus, greatly reduce performance degradation. Laser tests show that the threshold of the proposed divider can be significantly improved. The heavy-ion experiment shows good SET/single-event upset (SEU) tolerance during the ion strike under 83.7 MeV·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg.