2018 · 12 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyLeakage Power ReductionLow-noise Circuit DesignLow-power Digital Circuit DesignMemory DevicesLeakage PowerMemory Circuit DesignPower ConsumptionStatic Noise MarginStatic Random-access MemoryStatic Random-access Memory DesignUltra-low-power CmosUltra-low-voltage Circuit Design
In this paper, we present a novel disturb-free 10T static random access memory (SRAM) cell design for ultra-low power operations. It is well suited for bit-interleaving architecture which helps to improve the soft error immunity with error correction code. The write margin and read static noise margin of the cell are significantly improved due to its built-in write/read-assist scheme. The experimental results indicate that at a 0.4V supply voltage, RSNM and WM of the proposed 10T SRAM cell achieve 2.93× and 1.99× as that of the conventional 6T SRAM cell, respectively. Its leakage power consumption is reduced by 54.7% as compared with the conventional 6T SRAM cell in a 40-nm CMOS technology.
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Stable SRAM cell design for the 32 nm node and beyond
L. Chang, David Fried, J. M. Hergenrother et al. · 2005 · 567 citations
Engineering, Computer Engineering, Electrical Engineering +17