IEEE Journal of Solid-State Circuits · 2007 · 439 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ScalingLeakage Power ReductionLow-power Digital Circuit DesignPower ManagementVoltage ScalingLeakage PowerLow-power Memory ArchitectureLow-power Memory CircuitsLow-voltage Cmos DesignSub-threshold OperationThreshold Voltage ScalingUltra-low-voltage Circuit DesignVoltage Scaling In Memory Systems
Low‑voltage SRAM operation reduces leakage and active energy but increases design challenges. The paper investigates the limits of low‑voltage operation for conventional 6T SRAM and proposes an alternative bitcell that functions at much lower voltages. The authors evaluate the proposed bitcell on a 256‑kb 65‑nm SRAM test chip. Measurements show the test chip operates below 400 mV in sub‑threshold, delivering substantial power and energy savings at the expense of speed, and the paper presents detailed data and analysis of voltage‑scaling limits.
Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.
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A 256kb Sub-threshold SRAM in 65nm CMOS
Benton H. Calhoun, Anantha P. Chandrakasan · 2006 · 231 citations
Engineering, Computer Engineering, Electrical Engineering +17
SRAM leakage suppression by minimizing standby supply voltage
Yu Cao, Dejan Marković, Andrei Vladimirescu et al. · 2004 · 206 citations
Engineering, Computer Engineering, Electrical Engineering +17
Circuit and microarchitectural techniques for reducing cache leakage power
Nam Sung Kim, Krisztián Flautner, David Blaauw et al. · 2004 · 158 citations
Low-power embedded SRAM modules with expanded margins for writing
Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki et al. · 2005 · 136 citations
Engineering, Computer Engineering, Electrical Engineering +17