A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

TLDR

Low‑voltage SRAM operation reduces leakage and active energy but increases design challenges. The paper investigates the limits of low‑voltage operation for conventional 6T SRAM and proposes an alternative bitcell that functions at much lower voltages. The authors evaluate the proposed bitcell on a 256‑kb 65‑nm SRAM test chip. Measurements show the test chip operates below 400 mV in sub‑threshold, delivering substantial power and energy savings at the expense of speed, and the paper presents detailed data and analysis of voltage‑scaling limits.

Abstract

Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.