Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic

Abstract

In this paper, a high-speed power-efficient VLSI implementation of a finite field multiplier in GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) is presented. The proposed design has a serial-in parallel-out architecture and performs the multiplication operation using a reordered normal basis. The basic idea is to implement the main building block of the multiplier in domino logic to reduce the critical path delay. Reduction in dynamic power consumption is achieved by limiting the contention current between the keeper transistor and the pull-down network at the beginning of the evaluation phase by employing a new keeper control circuit. The semicustom layout of the multiplier was realized in 65-nm CMOS technology. The post place-and-route simulations showed that the multiplier can perform multiplication correctly up to a clock rate of 3.85 GHz and consumes marginally less power than the static CMOS counterpart (also implemented with custom placement and route). The size of the multiplier is currently recommended by the National Institute of Standards and Technology for binary field multiplication in elliptic curve cryptography. The proposed design methodology can also be used in the implementation of similar finite field multipliers possessing regular architectures.