Akashi Satoh - Concepedia

Author

Akashi Satoh

National Institute of Advanced Industrial Science and Technology

Also Known As

A. SATOH, A. Satoh, Akashi SATOH, Akashi Satoh

102

Publications

3.2K

Citations

H-Index

Concepts

All Affiliations

National Institute of Advanced Industrial Science and Technology Tohoku University University of Electro-Communications IBM Research - Tokyo IBM (United States)

About

Akashi Satoh is an author at National Institute of Advanced Industrial Science and Technology specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	21	37	1.7K
2	Computer Engineering	21	35	1.6K
3	Computer Science	17	22	1.1K
4	Public Health	1	1	14
5	Applied Physics	1	1	52

Akashi Satoh

Publications

1.7K

Citations

H-Index

Page 1

	Year	Citations
A scalable dual-field elliptic curve cryptographic processor Akashi Satoh, Kohji Takano IEEE Transactions on Computers Cryptographic PrimitiveEngineeringHardware AlgorithmComputer ArchitectureElliptic Curve	2003	248
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Hardware SecurityHardware TrojanElectrical EngineeringEngineeringComputer Engineering	2010	245
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture Sumio Morioka, Akashi Satoh IEEE Transactions on Very Large Scale Integration (VLSI) Systems Hardware SecurityData Encryption StandardEngineeringVlsi DesignVlsi Architecture	2004	97
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringComputer ArchitectureHardware SystemsHigh-radix Montgomery MultipliersRsa Processors	2010	86
An on-chip glitchy-clock generator for testing fault injection attacks Sho Endo, Takeshi Sugawara, Naofumi Homma, Journal of Cryptographic Engineering Hardware SecurityHardware TrojanReliability EngineeringEngineeringSoftware Testing	2011	81
A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture Sumio Morioka, Akashi Satoh EngineeringVlsi DesignComputer ArchitectureTwisted-bdd S-box ArchitectureBlock Cipher	2003	70
Side-channel AttacK User Reference Architecture board SAKURA-G Hendra Guntur, Jun Ishii, Akashi Satoh EngineeringInformation SecurityComputer ArchitectureSide-channel AttackHardware Security	2014	62
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS Akashi Satoh, Tadanobu Inoue Integration Hardware SecurityCryptographic PrimitiveEngineeringPerceptual HashingFormal Methods	2006	56
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays Yohei Hori, Hyunho Kang, Toshihiro Katashita, Journal of Information Processing Hardware SecurityDevice VariationsElectrical EngineeringHardware TrojanEngineering	2014	52
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates Miroslav Knežević, Kazuyuki Kobayashi, Jun Ikegami, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Fourteen Round TwoEngineeringHardware Verification LanguageVerificationComputer Architecture	2011	47

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