Normally Off Vertical 3-D GaN Nanowire MOSFETs With Inverted <inline-formula> <tex-math notation="LaTeX">${p}$ </tex-math> </inline-formula>-GaN Channel

Abstract

This paper reports on the normally off GaN vertical MOSFETs based on nanowires (NWs) with an inverted p-GaN channel and a wrap-around-gate structure for the first time. Both inductively coupled plasma dry reactive-ion etching and wet-chemical etching were employed to fabricate the vertically aligned GaN NWs from epitaxial thin films with a specified doping profile. During the wet etching, the influence of p-doping on the NW morphology was investigated, and the results could be explained by the proposed model. In comparison with other c-axis NW transistors, an enhancement-mode (E-mode) operation with a superior threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) of 2.5 V has been reached in the fabricated GaN MOSFETs. Furthermore, a high driving-current density of 101 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> as well as a high ON-/OFF-current ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> was obtained in the NWs, predicting a potential approach toward future GaN electronics with vertical and smart architecture.