Impact of Dielectric Pocket on Analog and High-Frequency Performances of Cylindrical Gate-All-Around Tunnel FETs

Abstract

In this paper, a novel structure of cylindrical GAA-TFETs with high-k dielectric pocket is proposed to improve the analog and high-frequency performances. We have discussed the device physics of proposed structure in details with the help of 3-D TCAD simulation. Since, an optimum part of the drain region is replaced with a high-k dielectric material (HfO2), oxide-semiconductor interface formed between channel and dielectric pocket increases the tunneling width at channel-drain junction. Further, this increment in tunneling width caused by depleted drain region under dielectric pocket eventually reduces the ambipolar conduction and OFF-current without deteriorating ON-current and subthreshold slope. It is observed that device performances are improved with increasing pocket length and thickness up to a value of 30-nm and 4-nm respectively; beyond which either device performances are degraded or dependences become poor. The advantages of using a high-k dielectric material over low-k are demonstrated in terms of reduction in ambipolar conduction, and immunity against degradation in current switching ratio during device scaling. Additionally, the impact of high-k dielectric pocket on high-frequency performances is demonstrated. Unlike tunnel FETs with dielectric spacer, it is observed that drain-to-gate capacitance is reduced for our proposed device which further leads to improvement in cutoff frequency.