2017 · 33 citations · 7 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsPackaging DesignSemiconductor DevicesChip PackagingDevice ReliabilityDielectric MaterialsDielectricsIntegrated Circuit DesignSemiconductor ReliabilityAdvanced PackagingDielectric StrengthElectrical ReliabilityElectromigrationMechanical ReliabilityPackage ReliabilityReliability DegradationReliability Degradation Mechanisms
Aggressive scaling down of the Cu trace pitch in the redistribution layer (RDL) is needed to meet the design rule for high-density I/O used in advanced packaging. Such a downsized RDL, however, will be vulnerable to voltage and current stresses, in addition to environmental stress. Voltage stress, for example, degrades the reliability of electrical isolation (dielectric strength). This will likely be a serious problem when the pitch of the Cu traces becomes less than 4 μm since Cu migration will become substantial due to a rapid increase in the electric field between traces. This means that the conventional RDL structure based on a semi-additive process may fail to meet the performance specified by the Joint Electron Device Engineering Council (JEDEC) reliability standard. A previously proposed enhanced RDL, in which the Cu traces are covered with two types of inorganic dielectrics, showed potential performance suitable for advanced packaging technologies in terms of both electrical and mechanical reliability. The Cu trace pitch has now been scaled down from 20 μm to as small as 2 μm. Characterization of this downsized redistribution layer in terms of electrical reliability using biased highly accelerated temperature and humidity stress testing and electromigration testing showed that the first inorganic dielectric completely suppressed Cu migration and Cu surface diffusion, which degrade electrical isolation and electromigration resistance, respectively. This downsized enhanced RDL is thus promising for advanced high-density fan-out wafer-level packaging and 2.5 D interposer packaging.
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InFO (Wafer Level Integrated Fan-Out) Technology
Chien-Fu Tseng, Chung-Shi Liu, Chi-Hsi Wu et al. · 2016 · 275 citations
J. R. Lloyd, Michael Lane, E. Liniger et al. · IEEE Transactions on Device and Materials Reliability · 2005 · 83 citations