Memory Performance of a Simple Pr_0.7Ca_0.3MnO₃-Based Selectorless RRAM

Abstract

Enhancement of nonlinearity (NL) in low-resistance state (LRS) currents of resistance random access memory (RRAM) devices is a key challenge for the selectorless RRAM array. The conventional approach is based on adding multiple dielectrics, e.g., tunnel layers to enable NL at the expense of stack simplicity. In this brief, we present a Pr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ca <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> MnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (PCMO)-based selectorless RRAM device that exhibits high NL. The presented single oxide layer device (W/PCMO/Pt) enables selectorless RRAM without an extra tunnel barrier layer. The demonstrated device is forming free. It shows a low SET current density (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and a high NL in LRS current for READ operation (105 ±5) and for SET operation (44±4) along with a large memory window (160±2) in dc cycling. Further, the device shows very low device-to-device variability (σ/μ <; 0.23) along with excellent retention (ten years at 200 °C), good pulsed endurance (no degradation for >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cycles), and a possible multilevel cell capability. A self-heating-based sharp current increase produces the NL to enable selectorless operation. Thus, a selectorless PCMO-based RRAM based on a novel mechanism is presentedand benchmarked against the literature.