EngineeringComputer EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingDevice ReliabilityDevice SimulationMemory ModelingSemiconductor ReliabilityCompact ModelingCycling EnduranceEnduranceEndurance CharacteristicsEndurance ModelingMetal-oxide-semiconductor Field-effect Transistor ModelingReliability SimulationTransient Device Modeling
A complete Spice-compatible model for stacked-gate flash EEPROM cells has been successfully developed. It includes an accurate DC I-V model, a gate current model for Channel Hot Electron (CHE) programming; and a channel Fowler-Nordheim (FN) current model for erase. Program and erase induced oxide damage are also included in the model. For the first time, it allows the simulation of the programming/erase transient and the P/E cycling endurance characteristics using the present analytical approach. It provides an easy way for applications to cell design optimization and reliability evaluation for device and circuit designers.
7