21 psec switching 0.1 μm-CMOS at room temperature using high performance Co salicide process

Abstract

In this paper we report a record of 0.1 /spl mu/m-CMOS switching delay of 21 psec per gate at room temperature operation. Good subthreshold characteristics are achieved for 0.1 pm gate length n-MOS and p-MOS. Conventional Ti, Pt and Co self-aligned silicide process (salicide) degraded the 0.1 pm CMOS switching delay because the gate sheet resistances increased at fine-line. In contrast, Co salicide with TiN capping process achieved a low gate resistance of 5 /spl Omegasq at all over gate length. And it allowed the high speed operation at the sub quarter micron gate length region.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>