Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies

Abstract

Alpha particle-induced flip-flop soft-error rates (SER) for 20-nm bulk planar and 16-nm bulk FinFET technologies are characterized over temperature with different supply voltages. Experimental results indicate that the 16-nm FinFET SER changes insignificantly with temperature while the 20-nm planar SER increases by ∼2x over the same temperature range. 3D TCAD and circuit-level simulations show changes in single-event transient (SET) pulse width and logic gate delay are the controlling factors, with opposing influences on SER.