Preliminary results on TFET — Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology

Abstract

The purpose of this paper is to introduce preliminary results on thin silicon film TFET (gated diode) topology in 28 nm FD-SOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models and on silicon measurements of different devices. It shows that the TFET is functional and could be enhanced for advanced IO and ESD design solutions.