G. Le Carval - Concepedia

Author

G. Le Carval

Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Also Known As

G Le Carval, G. Carval, G. Le Carval, Gilles Le Carval, Gilles le Carval, Le Carval, G., Le Carval, Gilles, M. Vinet

Publications

563

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives CEA Grenoble Laboratoire d'Électronique des Technologies de l'Information Institut polytechnique de Grenoble Université Grenoble Alpes

About

G. Le Carval is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in electrical engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	14	402
2	Electrical Engineering	12	13	383
3	Applied Physics	11	12	359
4	Computer Engineering	4	4	146
5	Natural Sciences	1	1	26

G. Le Carval

Publications

452

Citations

H-Index

Page 1

	Year	Citations
Further Insights in TFET Operation A. Villalon, G. Le Carval, Sébastien Martinie, IEEE Transactions on Electron Devices Electrical EngineeringEngineeringTunneling MicroscopyTunnel FetsElectronic Engineering	2014	69
Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit F. Mayer, C. Le Royer, G. Le Carval, IEEE Transactions on Electron Devices Dynamic Tcad AnalysisEngineeringImos PerformanceComputer ArchitectureIntegrated Circuits	2006	53
Investigation of Forming, SET, and Data Retention of Conductive-Bridge Random-Access Memory for Stack Optimization Jérémy Guy, G. Molas, P. Blaise, IEEE Transactions on Electron Devices Non-volatile MemoryEngineeringComputer ArchitectureConductive-bridge Random-access MemoryPhase Change Memory	2015	50
Experimental determination of the channel backscattering coefficient on 10–70nm-metal-gate Double-Gate transistors V. Barral, T. Poiroux, M. Vinet, Solid-State Electronics Semiconductor TechnologyElectrical EngineeringExperimental DeterminationEngineeringNanoelectronics	2007	35
105nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200mm GeOI wafers C. Le Royer, L. Clavelier, C. Tabone, Solid-State Electronics Electrical EngineeringGeoi WafersEngineeringNanoelectronicsApplied Physics	2008	30
Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology Maxime Rousseau, O. Rozeau, G. Cibrario, HAL (Le Centre pour la Communication Scientifique Directe)	2008	29
Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization J. Guy, G. Molas, P. Blaise, Cbram StackEngineeringEmerging Memory TechnologyConductive Bridge RamComputer Architecture	2014	26
Co-integration of 2 mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS F. Mayer, C. Le Royer, G. Le Carval, Proceedings of the European Solid State Device Research Conference Electrical EngineeringIon ImplantationEngineeringPhysicsNanoelectronics	2006	23
Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS) F. Mayer, C. Le Royer, G. Le Carval, Solid-State Electronics Impact Ionization MosElectrical EngineeringIon ImplantationEngineeringApplied Physics	2007	22
High-$\kappa$ and Metal-Gate pMOSFETs on GeOI Obtained by Ge Enrichment: Analysis of ON and OFF Performances C. Le Royer, Benjamin Vincent, L. Clavelier, IEEE Electron Device Letters EngineeringIntegrated CircuitsGe EnrichmentMetal-gate PmosfetsSemiconductor Device	2008	21

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