Publication | Closed Access
105nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200mm GeOI wafers
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Citations
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References
2008
Year
Electrical EngineeringGeoi WafersEngineeringNanoelectronicsApplied PhysicsSi Process LineSemiconductor Device FabricationGate Length PmosfetsMicroelectronicsSilicon On InsulatorSemiconductor Device
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