Optimization of Design Parameters in Dual-k Spacer-Based Nanoscale Reconfigurable FET for Improved Performance

Abstract

This paper reports various optimization aspects of an ambipolar silicon nanowire field-effect transistor with high-κ source-drain (S/D) spacer using coupled 3-D Technology Computer Aided Design numerical device simulations. The impact of variation in device features, such as spacer material type and length of spacer (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> ), gate dielectric and its thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> ) and intergate distance (d <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G1G2</sub> ) on vital performance parameters of the device, such as ION, ION/IOFF, Subthreshold swing (S/S), V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> , and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , is investigated and analyzed. It is observed that increasing the spacer length increases Band to band tunneling rate probability through the thin barriers at ON-state. Moreover, the permittivity of spacer material is found to be closely related to the lateral fringe lines emanated from gate, resulting in a boosted ION as well as g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> at higher κ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> . Scaling down the thickness of gate oxide is not found to be a good idea, as it causes a reduction in ON-OFF current ratio though S/S remains mostly unaffected. However, intergate distance scaling is found to have a strong influence on device performance providing higher current drive and lower S/S for both n- and p-programs at lower d <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G1G2</sub> .