Improved Short-Channel Characteristics With Long Data Retention Time in Extreme Short-Channel Flash Memory Devices

Abstract

Owing to the scaling demands, source/drain (S/D) junction engineering has evolved as a promising technique to improve the performance and reliability of NAND flash memory devices. In this paper, we investigate the impact of S/D doping lateral straggle σL on the program characteristics, data retention, and short-channel effects (SCEs) for sub-25-nm NAND flash memory device. Here, we consider threshold voltage roll-off, subthreshold slope, and drain-induced barrier lowering parameters to study the SCE for the aforementioned memory device. We also examine the effect of varying σL on the junction boost leakage current [during the program-inhibition (P-I) mode] for the considered device. Based on our investigations, we have shown that adjusting the S/D doping lateral straggle σL appropriately not only improves SCE but also the program speed and data retention without any need of altering the gate oxide stack. Furthermore, the junction boost leakage current also decreases on reducing σL. Consequently, it enables the device to hold high channel potential during the P-I mode, and thereby reduces the risk of false programming/erasing of the device.