IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005 · 20 citations · 17 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSystem-on-chip DesignClock ManagementDevice CharacterizationDevice ModelingSemiconductor ReliabilityTiming AnalysisTiming ModelingFailure ProbabilityFailure Probability AnalysisFailure Probability EstimationLeakage AnalysisLeakage PowerLeakage Power EstimationProcess Variation AnalysisSilicon
Inherent process device variations and fluctuations during manufacturing have a large impact on the microprocessor maximum clock frequency and total leakage power. These fluctuations have a statistical distribution that calls for usage of statistical methods for frequency and leakage analysis. This paper presents a simple technique for accurate estimation of product high-level (Full Chip) parameters such as the maximum frequency (FMAX) distribution and the total leakage (ISB). Moreover, this technique can grade critical paths by their failure probability and perform what-if analysis to estimate FMAX after fixing specific speed paths. Using our FMAX/ISB prediction, we show good correlation with silicon measurements from a production microprocessor.
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First-order incremental block-based statistical timing analysis
C. Visweswariah, Kaushik Ravindran, Kerim Kalafala et al. · 2004 · 661 citations