C. Visweswariah

First-order incremental block-based statistical timing analysis

C. Visweswariah, Kaushik Ravindran, Kerim Kalafala et al. · 2004 · 653 citations

Logic Synthesis, Arrival Times, Engineering +13

First-Order Incremental Block-Based Statistical Timing Analysis

C. Visweswariah, Kaushik Ravindran, Kerim Kalafala et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2006 · 226 citations

Hardware Security, Arrival Times, Physical Design (Electronics) +14

Statistical timing for parametric yield prediction of digital integrated circuits

J.A.G. Jess, Kerim Kalafala, Srinath R. Naidu et al. · 2003 · 128 citations

Engineering, Vlsi Design, Parametric Yield Prediction +16

Piecewise approximate circuit simulation

C. Visweswariah, R.A. Rohrer · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1991 · 92 citations

Numerical Analysis, Engineering, Simulation +17

Gradient-based optimization of custom circuits using a static-timing formulation

Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen et al. · 1999 · 91 citations

Electrical Engineering, Engineering, Vlsi Design +14