2003 · 398 citations · 18 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsStatistical ComputingSystem-on-chip DesignCircuit ComplexityDelay ModelingIntegrated Circuit DesignTiming AnalysisTiming ModelingCircuit Delay ModelingExponential Time ComplexityGate Delay ModelingPerformance VerificationProcess Variation AnalysisProcess Variation Delay ModelingStatistical Delay ModelingStatistical Timing Analysis
Process variations critically impact performance verification of high‑performance designs. The authors propose a linear‑time statistical timing analysis method that bounds the exact circuit delay while accounting for inter‑ and intra‑die variations and spatial correlations. They model inter‑ and intra‑die variations and spatial correlations, represent gate delays and arrival times as component sums, propagate and merge these to obtain an upper‑bound arrival‑time distribution, and implement the algorithm for benchmark testing. The bound is proven correct, can be tightened by multiple arrival‑time propagation, and achieves an average accuracy of 3.32% versus Monte Carlo simulation.
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for inter- and intra-die process variations and their spatial correlations. Since statistical timing analysis has an exponential run time complexity, we propose a method whereby a statistical bound on the probability distribution function of the exact circuit delay is computed with linear run time. First, we develop a model for representing inter- and intra-die variations and their spatial correlations. Using this model, we then show how gate delays and arrival times can be represented as a sum of components, such that the correlation information between arrival times and gate delays is preserved. We then show how arrival times are propagated and merged in the circuit to obtain an arrival time distribution that is an upper bound on the distribution of the exact circuit delay. We prove the correctness of the bound and also show how the bound can be improved by propagating multiple arrival times. The proposed algorithms were implemented and tested on a set of benchmark circuits under several process variation scenarios. The results were compared with Monte Carlo simulation and show an accuracy of 3.32% on average over all test cases.
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Delay variability: sources, impacts and trends
Sani Nassif · 2002 · 230 citations
Engineering, Computer Engineering, Electrical Engineering +17
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Jing-Jia Liou, Kwang‐Ting Cheng, Sandip Kundu et al. · 2001 · 147 citations
Engineering, Computer Engineering, Electrical Engineering +17
Statistical delay computation considering spatial correlations
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