2009 · 58 citations · 23 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignChip PackagingIntegrated Circuit DesignIntegrated Circuit DevicesInterconnect DesignInterconnect TechnologyWafer Bonding3D Integrated CircuitsAdvanced PackagingDevice MiniaturizationInterposer TechnologyMiniaturizationThree-dimensional IntegrationThrough-silicon Via PackagingThrough-silicon Vias
Moore's law has driven the IC industry to a billion transistor chip. But major technical and financial barriers are foreseen beyond 32 nm. One alternative path to this challenge seems to be stacked 3D ICs. But 3D ICs are a small part of any system and the total benefits of miniaturization cannot be realized until the entire system is miniaturized. This is the basis of 3D systems, the focus of this paper. The 3D miniaturization technologies briefly described in this paper include Si or wafer level interposers with Through-Package-Vias (TPV), nano-scale passives, thermal materials and interfaces and fine pitch system interconnections.
23
John Knickerbocker, Paul Andry, L.P. Buchwalter et al. · IBM Journal of Research and Development · 2005 · 236 citations
Engineering, Computer Engineering, Electrical Engineering +17