Self Heating Simulation of Multi-Gate FETs

Abstract

Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. This work demonstrates a simplification of the approach to a thermal only problem from which much useful information can be extracted. We have applied this approach to a typical trigate device on SOI substrate. The simulated thermal resistance is in reasonable agreement with measurements. Parameters for the width dependent compact model for the thermal resistance can readily be extracted. The dependence of thermal resistance on the thickness of the bottom oxide has also been investigated. Moreover this permits transient behavior to be simulated in much more detail than is possible to be measured experimentally. Thus time constants and thermal capacitances for thermal compact models which are usually difficult to extract experimentally may be simulated numerically