IEEE Electron Device Letters · 2008 · 123 citations · 10 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ScalingIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsThin-film TransistorsWide-bandgap Semiconductor DevicesChannel Doping EffectsCircuit OptimizationFin Field-effect Transistor ScalingFin Field-effect Transistors
The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> . We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> spacers, with kappa=20 spacers, we show that it is possible to achieve an 80% increase in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> at iso-I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> conditions and a 15% decrease in the inverter delay for a fan-out of four.
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Xuejue Huang, Wen‐Chin Lee, C. Kuo et al. · IEEE Transactions on Electron Devices · 2001 · 283 citations
Engineering, Electrical Engineering, Electronic Materials +15