MIX: a test generation system for synchronous sequential circuits

Abstract

We describe a test generation system for synchronous sequential circuits described at the gate level. The test generation system, called MIX, combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. It is known that different faults in a synchronous sequential circuit may be more amenable to different test generation approaches. The strength of MIX stems from the fact that a large number of different approaches is used to attack faults with different characteristics. Several new techniques are incorporated into MIX, including a new definition of an XD-frontier, storing a partial state transition graph to help in the derivation of justification sequences, utilization of sequences generated for aborted faults, consideration of multiple time frames simultaneously during state justification, and dynamic computation of dependencies among flip-flops. A simplified form of test generation under the restricted multiple observation times test strategy is also employed, based on state expansion. Restricted multiple observation times fault simulation is used in MIX to identify detected faults beyond those detected by conventional fault simulation.