Synchronous Sequential Logic is a type of digital circuitry in which the state transitions are coordinated by a global clock signal, ensuring that changes in output occur only at discrete time intervals determined by the clock.
158
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5.8K
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219
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89
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Publications per year
2017–2026
1
Parents
Publications
158
LUSTRE: A declarative language for programming synchronous systems*
Paul Caspi, D. Pilaud, Nicolas Halbwachs et al. · 1987 · 463 citations
1–5 of 158
Authors
219
- IP
24
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- SR
24
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- KCKwang‐Ting Cheng
University of California, Santa Barbara, United States
7 publications · 298 citations
7
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- MS
6
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- PP
6
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1–5 of 219
Institutions
89
University of Iowa
Iowa City, United States
24 h-index
94 publications
2.9K citations
AT&T (United States)
Bedminster, United States
12 h-index
19 publications
644 citations
Purdue University West Lafayette
West Lafayette, United States
10 h-index
11 publications
213 citations
University of California, Berkeley
Berkeley, United States
8 h-index
10 publications
183 citations
Lawrence Berkeley National Laboratory
Berkeley, United States
7 h-index
9 publications
248 citations
Cadence Design Systems (United States)
San Jose, United States
7 h-index
9 publications
465 citations
Politecnico di Torino
Turin, Italy
7 h-index
24 publications
804 citations
University of Illinois Urbana-Champaign
Urbana, United States
5 h-index
10 publications
622 citations
1–8 of 89
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
21 publications · 1K citations
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- IEEE Transactions on Computers
14 publications · 489 citations
13
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- IEEE Transactions on Electronic Computers
4 publications · 175 citations
4
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- Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
Conference · 3 publications · 89 citations
3
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- Electronics Letters
2 publications · 27 citations
2
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