Sequential Logic Description

Sequential Logic Description is a formal specification method within Hardware Description Languages that describes digital circuits with memory-dependent behavior, distinguishing itself from combinational logic descriptions by explicitly modeling state transitions over time.

732

Publications

37.8K

Citations

1.2K

Authors

437

Institutions

Publications per year

2017–2026

38

Authors

1.2K

  1. KC
    Kwang‐Ting Cheng

    University of California, Santa Barbara, United States

    30 publications · 2.1K citations

    23

    h-index

  2. SD
    Srinivas Devadas

    Massachusetts Institute of Technology, United States

    20 publications · 1K citations

    18

    h-index

  3. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    31 publications · 1.8K citations

    18

    h-index

  4. IP
    Irith Pomeranz

    University of Iowa, United States

    22 publications · 736 citations

    17

    h-index

  5. SR
    S.M. Reddy

    University of Iowa, United States

    23 publications · 901 citations

    17

    h-index

1–5 of 1.2K

Venues

  1. IEEE Transactions on Computers

    56 publications · 2.6K citations

    29

    h-index

  2. 29

    h-index

  3. IEEE Transactions on Electronic Computers

    17 publications · 962 citations

    16

    h-index

  4. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 9 publications · 309 citations

    9

    h-index

  5. IEEE Design & Test of Computers

    8 publications · 292 citations

    8

    h-index

1–5