Sequential Logic Description
Sequential Logic Description is a formal specification method within Hardware Description Languages that describes digital circuits with memory-dependent behavior, distinguishing itself from combinational logic descriptions by explicitly modeling state transitions over time.
732
Publications
37.8K
Citations
1.2K
Authors
437
Institutions
Publications per year
2017–2026
38
732
Synthesis and optimization of digital circuits
Choice Reviews Online · 1994 · 2.4K citations
Engineering, Computer Engineering, Electrical Engineering +17
SIS : A System for Sequential Circuit Synthesis
Ellen Sentovich · 1992 · 1.9K citations
Branching time and abstraction in bisimulation semantics
Rob J. van Glabbeek, W. P. Weijland · Journal of the ACM · 1996 · 737 citations · Full text
1–5 of 732
1.2K
University of California, Santa Barbara, United States
30 publications · 2.1K citations
23
h-index
18
h-index
18
h-index
17
h-index
17
h-index
1–5 of 1.2K
437
AT&T (United States)
Bedminster, United States
28 h-index
65 publications
4K citations
University of California, Berkeley
Berkeley, United States
26 h-index
119 publications
9.1K citations
University of Illinois Urbana-Champaign
Urbana, United States
23 h-index
53 publications
2.9K citations
Massachusetts Institute of Technology
Cambridge, United States
21 h-index
37 publications
2.4K citations
University of Iowa
Iowa City, United States
18 h-index
50 publications
2K citations
Princeton University
Princeton, United States
18 h-index
38 publications
1.4K citations
Carnegie Mellon University
Pittsburgh, United States
16 h-index
45 publications
5.2K citations
Nokia (United States)
Coppell, United States
16 h-index
27 publications
2.2K citations
1–8 of 437
56 publications · 2.6K citations
29
h-index
58 publications · 3.7K citations
29
h-index
17 publications · 962 citations
16
h-index
TODAES · 9 publications · 309 citations
9
h-index
8 publications · 292 citations
8
h-index
1–5