Finite State Machine Verification is a formal method for rigorously establishing the correctness of a finite state machine's behavior against a specified set of temporal or logical properties through algorithmic analysis.
390
Publications
28.4K
Citations
751
Authors
310
Institutions
Publications per year
2017–2026
38
Parents
Publications
390
Thomas A. Henzinger · 2002 · 1.9K citations
Automatic verification of probabilistic concurrent finite state programs
Moshe Y. Vardi · 1985 · 675 citations
1–5 of 390
Authors
751
- GS
11
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- AL
11
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- LA
10
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- MB
9
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- RK
8
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1–5 of 751
Institutions
310
University of California, Berkeley
Berkeley, United States
13 h-index
47 publications
3.5K citations
University of Massachusetts Amherst
Amherst Center, United States
12 h-index
39 publications
3.4K citations
Imperial College London
London, United Kingdom
11 h-index
33 publications
1.8K citations
Carnegie Mellon University
Pittsburgh, United States
10 h-index
25 publications
8.9K citations
AT&T (United States)
Bedminster, United States
10 h-index
17 publications
1.5K citations
The University of Texas at Austin
Austin, United States
9 h-index
15 publications
3.8K citations
Centre National de la Recherche Scientifique
Paris, France
7 h-index
12 publications
592 citations
University of Kaiserslautern
Kaiserslautern, Germany
7 h-index
16 publications
221 citations
1–8 of 310
Venues
- IEEE Transactions on Automatic Control
9 publications · 710 citations
10
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- Formal Methods in System Design
8 publications · 233 citations
9
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- Electronic Notes in Theoretical Computer Science
ENTCS · 9 publications · 207 citations
9
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- Information and Computation
8 publications · 320 citations
8
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
8 publications · 333 citations
8
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