Hardware Description Languages
Hardware Description Language is a formal language used to specify the structure and behavior of digital hardware systems at multiple levels of abstraction to facilitate design, simulation, verification, and synthesis.
4.7K
Publications
172.3K
Citations
10.2K
Authors
1.8K
Institutions
Publications per year
2017–2026
527
Variants
Hardware Description LanguageHdlHdls
Parents
4.7K
Synthesis and optimization of digital circuits
Choice Reviews Online · 1994 · 2.4K citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 4.7K
10.2K
École Polytechnique Fédérale de Lausanne, Switzerland
30 publications · 2K citations
21
h-index
19
h-index
Massachusetts Institute of Technology, United States
20 publications · 1.4K citations
18
h-index
18
h-index
18
h-index
1–5 of 10.2K
1.8K
Stanford University
Stanford, United States
40 h-index
213 publications
12.9K citations
University of California, Berkeley
Berkeley, United States
37 h-index
225 publications
11.6K citations
Carnegie Mellon University
Pittsburgh, United States
34 h-index
160 publications
11.3K citations
Massachusetts Institute of Technology
Cambridge, United States
30 h-index
104 publications
4.4K citations
University of Illinois Urbana-Champaign
Urbana, United States
30 h-index
173 publications
13.3K citations
IBM (United States)
Armonk, United States
30 h-index
114 publications
8.2K citations
Politecnico di Torino
Turin, Italy
29 h-index
164 publications
6.3K citations
Princeton University
Princeton, United States
29 h-index
141 publications
5K citations
1–8 of 1.8K
193 publications · 11.1K citations
52
h-index
96 publications · 5.8K citations
41
h-index
77 publications · 2.9K citations
32
h-index
37 publications · 2.9K citations
27
h-index
51 publications · 2.9K citations
25
h-index
1–5
See also Hardware Description Languages | |
|---|---|
Language Constructs | |
Design Flow | Hardware Description Languages High-level Synthesis Domain-specific Languages Formal Specifications Proof Assistants Simulation Studies |
Verification Techniques | Formal Verification Model Checking Equivalence Checking Simulation-based Verification Assertion-based Verification Theorem Proving Testbenches Symbolic Verification Hardware Assertion Languages |
Language Families | Domain-specific Languages Compiler-based High-level Synthesis Hardware Generation Vhdl System Verilog |