Assertion-based Verification
Assertion-Based Verification is a hardware verification methodology that employs formal assertions—embedded within a Hardware Description Language—to specify intended behaviors and automatically detect deviations, thereby enabling dynamic or static validation of functional correctness.
774
Publications
34.1K
Citations
1.7K
Authors
556
Institutions
Publications per year
2017–2026
100
774
Gerwin Klein, Kevin Elphinstone, Gernot Heiser et al. · 2009 · 1.6K citations
Gordon Fraser, Andrea Arcuri · 2011 · 1K citations
Gary T. Leavens, Albert L. Baker, Clyde Ruby · ACM SIGSOFT Software Engineering Notes · 2006 · 787 citations
1–5 of 774
1.7K
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University of Illinois Urbana-Champaign, United States
11 publications · 471 citations
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8
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1–5 of 1.7K
556
The University of Texas at Austin
Austin, United States
19 h-index
37 publications
2.5K citations
Microsoft (United States)
Redmond, United States
17 h-index
25 publications
1.6K citations
Stanford University
Stanford, United States
16 h-index
30 publications
1.8K citations
University of Illinois Urbana-Champaign
Urbana, United States
16 h-index
59 publications
3.6K citations

Centre National de la Recherche Scientifique
Paris, France
15 h-index
55 publications
1.7K citations
Carnegie Mellon University
Pittsburgh, United States
14 h-index
30 publications
1.4K citations
Intel (United States)
Santa Clara, United States
14 h-index
32 publications
932 citations
University of California, Berkeley
Berkeley, United States
13 h-index
32 publications
1.1K citations
1–8 of 556
21 publications · 844 citations
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14 publications · 643 citations
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13 publications · 879 citations
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TSE · 15 publications · 1.7K citations
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ENTCS · 11 publications · 635 citations
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