Assertion-based Verification

Assertion-Based Verification is a hardware verification methodology that employs formal assertions—embedded within a Hardware Description Language—to specify intended behaviors and automatically detect deviations, thereby enabling dynamic or static validation of functional correctness.

774

Publications

34.1K

Citations

1.7K

Authors

556

Institutions

Publications per year

2017–2026

100

Authors

1.7K

  1. GP
    Graziano Pravadelli

    University of Verona, Italy

    14 publications · 352 citations

    12

    h-index

  2. SV
    Shobha Vasudevan

    University of Illinois Urbana-Champaign, United States

    11 publications · 471 citations

    11

    h-index

  3. ŽŽ
    Željko Žilić

    McGill University, Canada

    8 publications · 330 citations

    8

    h-index

  4. RL
    Ralph L. London

    The University of Texas at Austin, United States

    8 publications · 339 citations

    8

    h-index

  5. PD
    Pallab Dasgupta

    Indian Institute of Technology Kharagpur, India

    7 publications · 169 citations

    7

    h-index

1–5 of 1.7K

Venues

  1. ACM SIGPLAN Notices

    21 publications · 844 citations

    15

    h-index

  2. Science of Computer Programming

    14 publications · 643 citations

    13

    h-index

  3. 12

    h-index

  4. IEEE Transactions on Software Engineering

    TSE · 15 publications · 1.7K citations

    12

    h-index

  5. Electronic Notes in Theoretical Computer Science

    ENTCS · 11 publications · 635 citations

    11

    h-index

1–5