System Verilog is a hardware description and verification language that extends Verilog with advanced constructs for modeling, testing, and verifying complex digital systems at multiple levels of abstraction.
226
Publications
8.1K
Citations
663
Authors
193
Institutions
Publications per year
2017–2026
40
Variants
Systemverilog
Parents
Publications
226
1–5 of 226
Authors
663
- İH
14
h-index
- DK
5
h-index
- EK
5
h-index
- AA
4
h-index
- MH
4
h-index
1–5 of 663
Institutions
193
Sabancı Üniversitesi
Istanbul, Türkiye
14 h-index
41 publications
1.1K citations
Stanford University
Stanford, United States
8 h-index
23 publications
1.4K citations
Massachusetts Institute of Technology
Cambridge, United States
7 h-index
14 publications
356 citations
Carnegie Mellon University
Pittsburgh, United States
7 h-index
16 publications
1.2K citations
Intel (United States)
Santa Clara, United States
5 h-index
13 publications
267 citations
The University of Texas at Austin
Austin, United States
4 h-index
8 publications
256 citations
Concordia University
Montreal, Canada
4 h-index
11 publications
150 citations
Vellore Institute of Technology University
Vellore, India
4 h-index
8 publications
114 citations
1–8 of 193
Venues
- IEEE Transactions on Consumer Electronics
9 publications · 249 citations
9
h-index
- Microelectronics Journal
3 publications · 167 citations
3
h-index
- ACM SIGARCH Computer Architecture News
3 publications · 76 citations
3
h-index
- Proceedings - ACM IEEE Design Automation Conference
3 publications · 67 citations
3
h-index
- Journal of Physics Conference Series
2 publications · 36 citations
2
h-index
1–5