Hardware Assertion Languages

Hardware Assertion Languages is a formal specification language used in digital design verification that enables the expression of temporal properties and behavioral constraints at the register-transfer level, distinguishing it from general-purpose hardware description languages by its focus on assertion-based verification and property checking.

21

Publications

716

Citations

67

Authors

27

Institutions

Publications per year

2017–2026

3

Authors

67

  1. MP
    Mark P. Jones

    Yale University, United States

    2 publications · 82 citations

    2

    h-index

  2. PD
    Pallab Dasgupta

    Indian Institute of Technology Kharagpur, India

    2 publications · 86 citations

    2

    h-index

  3. AT
    Andrew Tolmach

    Portland State University, United States

    2 publications · 82 citations

    2

    h-index

  4. TH
    Thomas Hallgren

    Sahlgrenska University Hospital, Sweden

    2 publications · 82 citations

    2

    h-index

  5. RL
    Rebekah Leslie

    Portland State University, United States

    2 publications · 82 citations

    2

    h-index

1–5 of 67

Venues

  1. IEEE Design & Test of Computers

    2 publications · 139 citations

    2

    h-index

  2. ACM SIGPLAN Notices

    1 publications · 11 citations

    1

    h-index

  3. Computers & Electrical Engineering

    1 publications · 11 citations

    1

    h-index

  4. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 1 publications · 28 citations

    1

    h-index

  5. Journal of Systems and Software

    JSS · 1 publications · 20 citations

    1

    h-index

1–5