Synthesis of System Verilog Assertions

TLDR

Assertion‑based verification has become a key technology for pre‑silicon validation of system‑on‑chip designs, and System Verilog integrates assertion specification directly with hardware description. This paper demonstrates the advantages of synthesizing assertions in hardware and proposes an approach for synthesizing System Verilog assertions (SVA) in hardware. The authors decompose SVA properties into simple communicating parallel hardware units that act as monitors, and provide a tool that implements this synthesis. The tool shows that the monitors for an industry‑standard ABV IP for the ARMAMBA AHB protocol occupy only modest chip area.

Abstract

In recent years, assertion-based verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip (SOC) designs. The System Verilog language integrates the specification of assertions with the hardware description. In this paper we show that there are several compelling reasons for synthesizing assertions in hardware, and present an approach for synthesizing System Verilog assertions (SVA) in hardware. Our method investigates the structure of SVA properties and decomposes them into simple communicating parallel hardware units that together act as a monitor for the property. We present a tool that performs this synthesis, and also show that the chip area required by the monitors for a industry standard ABV IP for the ARMAMBA AHB protocol is quite modest