Clocked Logic
Clocked Logic is a sequential logic design methodology in which state transitions and signal propagation within a digital circuit are synchronized to the rising or falling edges of a global clock signal, distinguishing it from asynchronous logic by enforcing temporal regularity through periodic timing control.
66
Publications
2.5K
Citations
201
Authors
72
Institutions
Publications per year
2017–2026
4
Variants
Synchronous Logic
Parents
66
R.H. Mathews, J.P. Sage, T. C. L. G. Sollner et al. · Proceedings of the IEEE · 1999 · 206 citations
Engineering, Computer Engineering, Electrical Engineering +17
Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment
Koji Kotani, T. Shibata, Makoto Imai et al. · 2002 · 97 citations
Engineering, Computer Engineering, Electrical Engineering +17
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72

University of Notre Dame
Notre Dame, United States
6 h-index
35 publications
2.3K citations
Laboratoire d'Électronique des Technologies de l'Information
Grenoble, France
5 h-index
11 publications
298 citations
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
Paris, France
5 h-index
11 publications
298 citations
Institut polytechnique de Grenoble
Grenoble, France
5 h-index
11 publications
298 citations

Université Grenoble Alpes
Saint-Martin-d'Hères, France
5 h-index
11 publications
298 citations
CEA Grenoble
Grenoble, France
5 h-index
11 publications
298 citations
University of California, Davis
Davis, United States
4 h-index
9 publications
376 citations
University of Utah
Salt Lake City, United States
3 h-index
6 publications
168 citations
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4 publications · 332 citations
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4 publications · 230 citations
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3 publications · 48 citations
3
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4 publications · 130 citations
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2 publications · 42 citations
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