Comprehensively study of read disturb immunity and optimal read scheme for high speed HfOx based RRAM with a Ti layer

Abstract

Although a significant effort was made recently in the development of binary oxide based resistive memory (RRAM), reliability issue is still the most concern, but less addressed. By stressing the device in high resistance state (HRS) with constant voltage of the same bias polarity during SET process, the disturbed time is found to exhibit extreme low Weibull slope (~0.3). This characteristic can drastically shrink the reliability margin for reading process. Inserting a thin Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> between the transition metal oxide and bottom electrode was proposed previously to improve read disturb immunity at room temperature. However, the effect of high temperature (125°C) on the read disturb of this stacked layer (HfOx/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) has not yet been studied. In this work, the degradation behavior of resistance state in the Ti/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> based resistive memory induced by constant voltage stress (CVS) is studied comprehensively. An improved reading scheme for the bipolar RRAM is proposed. For the requirement of high speed operation and robust read disturb for the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> based resistive memory with a Ti layer, a new and optimal film stack sequence (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti) was fabricated. The memory performances of the new stacked layer with different Ti thickness are also presented.