IEEE Transactions on Electron Devices · 1995 · 63 citations · 20 references
EngineeringElectrical EngineeringPhysicsMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice CharacterizationDevice ModelingDevice SimulationIntegrated Circuit DesignSemiconductor Device MaterialsSemiconductor PhysicsChannel Length ScalingDifferential ResistanceGate Oxide Thickness EffectsMetal-oxide-semiconductor Field-effect Transistor ModelingPredicationQuasi-two-dimensional ModelingSelf-heating Modeling
This paper reports a closed-form analytical drain current model considering both electron and lattice temperatures simultaneously using a quasi-two-dimensional approach for deep submicron ultrathin SOI NMOS devices. As verified by the experimental data, the closed-form analytical model shows a good predication of the negative differential resistance behavior. Based on the analytical model, with a channel length of <0.2 /spl mu/m, both the effective electron temperature and the lattice temperature are important in determining the negative differential resistance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Measurement and modeling of self-heating in SOI nMOSFET's
L.T. Su, J.E. Chung, D.A. Antoniadis et al. · IEEE Transactions on Electron Devices · 1994 · 331 citations
Physical origin of negative differential resistance in SOI transistors
Liam McDaid, Steven Hall, Phil Mellor et al. · Electronics Letters · 1989 · 118 citations
Engineering, Electrical Engineering, Condensed Matter Physics +15