Reducing leakage energy in FPGAs using region-constrained placement

TLDR

FPGAs are increasingly used across many applications, but as designs shrink to 90 nm and below, leakage power has become a critical concern that must be addressed as a primary optimization goal. This work proposes a leakage‑saving approach that partitions the FPGA fabric into small regions and selectively powers them on or off with sleep transistors, coupled with a placement strategy that maximizes the number of supply‑gated regions. Regions unused by the placed design are supply‑gated, and the technique is further extended to exploit temporal idleness within different parts of the same design. Experiments on commercial and academic designs with varying region sizes show that the proposed method outperforms conventional placement and significantly reduces leakage power.

Abstract

FPGAs are being increasingly used in a wide variety of applications. While power optimization has been only of secondary importance in many FPGA applications, growing importance of leakage in FPGAs designed in 90nm and below makes it imperative to treat power optimization as a first class citizen. In this paper, we propose a leakage-saving technique for FPGAs that involves dividing the FPGA fabric into small regions and switching on/off the power supply to each region using a sleep transistor in order to conserve leakage energy. Specifically, the regions not used by the placed design are supply gated. Next, we present a new placement strategy to increase the number of regions that can be supply gated. Finally, the supply gating technique is extended to exploit idleness in different parts of the same design during different time periods. Our experiments with different region sizes using various commercial and academic designs indicate that the proposed optimization outperforms conventional placement, and reduces leakage power consumption significantly.