Dynamic power consumption in Virtex™-II FPGA family

TLDR

The study focuses on Xilinx Virtex‑II FPGAs, the latest and largest programmable fabric. The paper analyzes dynamic power consumption in FPGA fabric using simulation and measurement. The authors identify key FPGA resources, measure their utilization from real designs, compute switching activity via case studies, and combine effective capacitance with utilization and activity to estimate each resource’s power share. They find routing, logic, and clocking consume 60 %, 16 %, and 14 % of power, and a Virtex‑II CLB dissipates about 5.9 µW per MHz, though it varies with switching activity.

Abstract

This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9μW per MHz for typical designs, but it may vary significantly depending on the switching activity.