EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSystem-on-chip DesignDelay ModelingIntegrated Circuit DesignInterconnect TechnologySignal IntegrityTiming AnalysisTiming ModelingCurrent Flow ModelingInterconnect Capacitance ModelingInterconnect Delay AnalysisInterconnect Delay ModelingInterconnect ModelingLumped Capacitance AnalysisSignal Integrity AnalysisTiming Characterization
In order to adequately account for nanometer effects during timing analysis, archaic standard cell models must be replaced. Simplifying assumptions used during characterization, such as nearly linear voltage inputs or lumped-capacitance loads, are no longer valid. Signal integrity analysis further complicates the characterization process because the typical voltage waveform used during characterization does not contain a noise component. This paper introduces two new technologies for standard cell and interconnect timing analysis: Blade and Razor. Blade is a novel cell model and runtime engine based on current flow. Razor is the accompanying interconnect model. Both Blade and Razor produce and consume arbitrary voltage waveforms with near-SPICE accuracy at speeds tens of thousands of times faster than SPICE.
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A gate-delay model for high-speed CMOS circuits
Florentin Dartu, Noel Menezes, Jessica Qian et al. · 1994 · 115 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17