A gate-delay model for high-speed CMOS circuits

Abstract

As signal speeds increase and gate delays decrease for high-perform ance digital integrated circuits, the gate delay m odeling problem becom es increasingly m ore difficult. With scaling, increasing interconnect resistances and decreasing gateoutput im pedances m ake it m ore difficult to em pirically characteriz e gate-delay m odels. Moreover, the single-input-switching assum ption for the em pirical m odels is incom patible with the inevitable sim ultaneous switching for todays high-speed logic paths.