Interconnect Capacitance Modeling
Interconnect Capacitance Modeling is an academic method that formulates the electrical capacitance of on-chip interconnect structures by combining geometric and material properties through analytical, numerical, or empirical techniques to enable accurate circuit performance prediction in integrated circuit design.
290
Publications
12.2K
Citations
738
Authors
208
Institutions
Publications per year
2017–2026
14
Parents
290
Jie Deng, H.‐S. Philip Wong · IEEE Transactions on Electron Devices · 2007 · 744 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 290
738
15
h-index
7
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7
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6
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5
h-index
1–5 of 738
208
Tsinghua University
Beijing, China
15 h-index
64 publications
1.4K citations
Georgia Institute of Technology
Atlanta, United States
11 h-index
25 publications
1K citations
Carnegie Mellon University
Pittsburgh, United States
10 h-index
19 publications
1.3K citations
IBM (United States)
Armonk, United States
10 h-index
17 publications
709 citations
Texas Instruments (United States)
Dallas, United States
10 h-index
41 publications
1.9K citations
IMEC
Leuven, Belgium
10 h-index
55 publications
2.7K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
10 h-index
23 publications
874 citations
Hewlett-Packard (United States)
Palo Alto, United States
9 h-index
22 publications
507 citations
1–8 of 208
23 publications · 1.1K citations
19
h-index
22 publications · 2.3K citations
18
h-index
16 publications · 656 citations
14
h-index
9 publications · 634 citations
9
h-index
8 publications · 228 citations
8
h-index
1–5