Interconnect Capacitance Modeling

Interconnect Capacitance Modeling is an academic method that formulates the electrical capacitance of on-chip interconnect structures by combining geometric and material properties through analytical, numerical, or empirical techniques to enable accurate circuit performance prediction in integrated circuit design.

290

Publications

12.2K

Citations

738

Authors

208

Institutions

Publications per year

2017–2026

14

Authors

738

  1. WY
    Wenjian Yu

    Tsinghua University, China

    19 publications · 446 citations

    15

    h-index

  2. EG
    Eby G. Friedman

    University of Rochester, United States

    7 publications · 350 citations

    7

    h-index

  3. AB
    Andrew B. Kahng

    University of California San Diego, United States

    7 publications · 302 citations

    7

    h-index

  4. LT
    Lawrence T. Pileggi

    Carnegie Mellon University, United States

    6 publications · 542 citations

    6

    h-index

  5. NA
    N.D. Arora

    Digital Wave (United States), United States

    5 publications · 234 citations

    5

    h-index

1–5 of 738

Venues

  1. 19

    h-index

  2. IEEE Transactions on Electron Devices

    22 publications · 2.3K citations

    18

    h-index

  3. 14

    h-index

  4. IEEE Electron Device Letters

    9 publications · 634 citations

    9

    h-index

  5. IEEE Transactions on Advanced Packaging

    8 publications · 228 citations

    8

    h-index

1–5